Publications
620 results found
Thomas DB, Luk W, 2007, Sampling from the Multivariate Gaussian distribution using reconfigurable hardware, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 3-+
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- Citations: 10
Juvonen MPT, Coutinho JGF, Luk W, 2007, Hardware architectures for adaptive background modelling, 2007 3RD SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS, Pages: 149-+
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- Citations: 4
Fidjeland A, Luk W, 2006, Archlog: High-level synthesis of reconfigurable multiprocessors for logic programming, Pages: 335-340
This paper presents Archlog, a language and framework for designing multiprocessor architectures in the logic programming domain. Our goal is to enable application developers in areas such as machine learning and cognitive robotics to produce high-performance designs for reconfigurable devices, without detailed knowledge of hardware development. The Archlog framework provides a high level of abstraction, enabling rapid system generation while supporting high performance. In this paper we present the Archlog language and its library-based compilation framework, which makes use of a customisable logic programming processor. The system generates multiple designs, with different trade-offs in the use of reconfigurable logic and embedded memories. An implementation of a multiprocessor for the machine learning system Progol on a 40MHz XC2V6000 FPGA is 10 times faster than a 2GHz Pentium 4 processor. © 2006 IEEE.
Derbyshire A, Becker T, Luk W, 2006, Incremental elaboration for run-time reconfigurable hardware designs, Pages: 93-102
We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in application specific integrated circuits (ASICs) or microprocessors. These systems can often provide substantially more computational power than microprocessors and support higher exibility than ASICs. The compilation of hardware during run time, however, can add significant run-time overhead to these systems. We introduce a novel compilation technique called incremental elaboration, which enables circuits to be dynamically generated during run time. We propose a set-based model for incremental elaboration, and explain how it can be used in the hardware compilation process. Our approach is illustrated by various designs, particulary those for pattern matching and shape-adaptive template matching. Copyright 2006 ACM.
Pell O, Luk W, 2006, Compiling higher-order polymorphic hardware descriptions into parametrised vhdl libraries with flexible placement information, Pages: 125-130
We present a framework for generating parametrised high-performance IP library cores from high level descriptions. Our system is based around the Quartz language which provides advanced features such as polymorphism, overloading, higher-order combinators and formal reasoning while supporting precise and flexible control of layout for efficient FPGA design and compiling into parametrised VHDL libraries. We illustrate the application of our system to the design of several example circuits; placement constraints generated by our system can increase clock frequency by up to 25% and can also reduce area. Quartz placement information is flexible, allowing us to easily describe placed circuits which can be compacted when specialised for particular input values. We describe a self-specialising multiplier which adjusts component locations when some input bits are known; this multiplier can be easily integrated into larger circuits such as FIR filters or matrix multipliers. © 2006 IEEE.
Ang S-S, Constantinides GA, Luk W, et al., 2006, The Cost of Data Dependence in Motion Vector Estimation for Reconfigurable Platforms, Pages: 333-336
Bayliss S, Bouganis C, Constantinides GA, et al., 2006, An FPGA Implementation of the Simplex Algorithm, Pages: 49-55
Lee D, Abdul Gaffar A, Cheung C, et al., 2006, Accuracy Guaranteed Bit-Width Optimization, IEEE Transactions on Computer-Aided Design, Vol: 25, Pages: 1990-2000, ISSN: 0278-0070
Mak S T, Sedcole N P, Cheung, et al., 2006, On-FPGA Communication Architectures and Design Factors, IEEE International Conference on Field-Programmable Logic, Pages: 161-168
Mak S T, Sedcole N P, Cheung, et al., 2006, On-FPGA Communication Architectures and Design Factors, IEEE International Conference on Field-Programmable Logic, Pages: 161-168
McKeever S, Luk W, 2006, Provably-correct hardware compilation tools based on pass separation techniques, FORMAL ASPECTS OF COMPUTING, Vol: 18, Pages: 120-142, ISSN: 0934-5043
Lee DU, Villasenor JD, Luk W, et al., 2006, A hardware Gaussian noise generator using the Box-Muller method and its error analysis, IEEE TRANSACTIONS ON COMPUTERS, Vol: 55, Pages: 659-671, ISSN: 0018-9340
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- Citations: 80
Dimond R, Mencer O, Luk W, 2006, Application-specific customisation of multi-threaded soft processors, 15th International Conference on Field Programmable Logic and Applications, Publisher: INST ENGINEERING TECHNOLOGY-IET, Pages: 173-180, ISSN: 1350-2387
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- Citations: 13
Todman TJ, Constantinides GA, Wilton SJE, et al., 2006, Reconfigurable computing: Architectures and design methods, System-on-Chip: Next Generation Electronics, Pages: 451-494, ISBN: 9780863415524
This chapter surveys two aspects of reconfigurable computing: architectures and design methods. The main trends in architectures are coarse-grained fabrics, heterogeneous functions and soft cores. The main trends in design methods are special purpose design methods, low power techniques and high-level transformations. We wonder what a survey of reconfigurable computing, written in 2015, will cover?.
Todman T J, Constantinides G A, Wilton, et al., 2006, Reconfigurable Computing: Architectures and Design Methods, System-on-Chip: Next Generation Electronics, Editors: Al-Hashimi, Publisher: IEE Press
Ang S-S, Constantinides GA, Luk W, et al., 2006, A Flexible Multi-Port Caching Scheme for Reconfigurable Platforms, Pages: 205-216
Thomas DB, Luk W, 2006, Non-uniform random number generation through piecewise linear approximations, 16th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 233-238, ISSN: 1946-1488
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- Citations: 1
Dimond RG, Mencer O, Luk W, 2006, CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools, International Conference on Field Programmable Logic (FPL), Tampere, Aug. 2005
Dimond R, Mencer O, Luk W, 2006, Automating processor customisation: Optimised memory access and resource sharing, Design, Automation and Test in Europe Conference and Exhibition (DATE 06), Publisher: IEEE, Pages: 204-+, ISSN: 1530-1591
Fu H, Mencer O, Luk W, 2006, Comparing floating-point and logarithmic number representations for reconfigurable acceleration, 5th IEEE International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 337-+
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- Citations: 6
Thomas DB, Bower JA, Luk W, 2006, Hardware architectures for Monte-Carlo based financial simulations, 5th IEEE International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 377-+
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- Citations: 9
Thomas DB, Luk W, 2006, Efficient hardware generation of random variates with arbitrary distributions, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 57-+
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- Citations: 8
Bower J, Luk W, Mencer O, et al., 2006, An SoC with Reconfigurable Debug Infrastructure
Sedcole P, Cheung PYK, Constantinides GA, et al., 2006, On-Chip Communication in Run-Time Assembled Reconfigurable Systems, Pages: 168-176
Bower JA, Thomas DB, Luk W, et al., 2006, <bold>A Reconfigurable Simulation Framework for Financial Computation</bold>, 3rd IEEE International Conference on Reconfigurable Computing and FPGAs, Publisher: IEEE, Pages: 30-+
Ang SS, Constantinides GA, Luk W, et al., 2006, A flexible multi-port caching scheme for reconfigurable platforms, Proc. Applied Reconfigurable Computing
Todman, Constantinides GA, Wilton SJE, et al., 2006, Reconfigurable Computing: Architectures and Design Methods
Lee D-U, Cheung RCC, Villasenor JD, et al., 2006, Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation, 5th IEEE International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 33-39
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- Citations: 17
DeFigueiredo Coutinho J, juvonen M, Wang J, et al., 2006, Designing a Posture Analysis System with Hardware Implementation, Journal of VLSI Signal Processing
DeFigueiredo Coutinho J, juvonen M, Wang J, et al., 2006, Designing a Posture Analysis System with Hardware Implementation, Journal of VLSI Signal Processing
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