Imperial College London
Professor Wayne Luk

ProfessorWayneLuk

Faculty of Engineering, Department of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Publication Type
Year
to

620 results found

Atasu K, Dimond RG, Mencer O, Luk Wet al., 2006, Towards Optimal Custom Instruction Processors, IEEE HOT Chips Conference, Stanford, August 2006

Conference paper

Bower J, Luk W, Mencer O, Flynn MJ, Morf Met al., 2006, Dynamic clock-frequencies for FPGAs, MICROPROCESSORS AND MICROSYSTEMS, Vol: 30, Pages: 388-397, ISSN: 0141-9331

Journal article

Yusuf S, Luk W, Szeto MKN, Osborne Wet al., 2006, UNITE: Uniform hardware-based network intrusion deTection engine, 2nd International Workshop on Reconfigurable Computing, Publisher: SPRINGER-VERLAG BERLIN, Pages: 389-400, ISSN: 0302-9743

Conference paper

Ho CH, Leong PHW, Luk W, Wilton SJE, Lopez-Buedo Set al., 2006, Virtual embedded blocks: A methodology for evaluating embedded elements in FPGAs, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 35-+

Conference paper

Dimond R, Mencer O, Luk W, 2006, Automating Processor Customisation: Optimised Memory Access and Resource Sharing, 2006 Design, Automation and Test in Europe, Publisher: IEEE

Conference paper

Pell O, Luk W, 2006, Generating parametrised hardware libraries from higher-order descriptions, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 297-+

Conference paper

Thomas DB, Luk W, 2006, Non-Uniform Random Number Generation Through Piecewise Linear Approximations., Publisher: IEEE, Pages: 1-6

Conference paper

Fahmy SA, Bouganis C-S, Cheung PYK, Luk Wet al., 2006, Efficient Realtime FPGA Implementation of the Trace Transform., Publisher: IEEE, Pages: 1-6

Conference paper

Fahmy SA, Bouganis C-S, Cheung PYK, Luk Wet al., 2006, Efficient realtime FPGA implementation of the Trace Transform, 16th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 555-560, ISSN: 1946-1488

Conference paper

Rissa T, Cheung PYK, Luk W, 2006, System level design exploration of JPEG 2000 with SoftSONIC virtual hardware platform, 49th IEEE International Midwest Symposium on Circuits and Systems, Publisher: IEEE, Pages: 276-+, ISSN: 1548-3746

Conference paper

Pell O, Luk W, 2006, <bold>COMPILING HIGHER-ORDER POLYMORPHIC HARDWARE DESCRIPTIONS INTO PARAMETRISED VHDL LIBRARIES WITH FLEXIBLE PLACEMENT INFORMATION</bold>, 16th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 125-130, ISSN: 1946-1488

Conference paper

Fidjeland A, Luk W, 2006, Archlog: High-level synthesis of reconfigurable multiprocessors for logic programming, 16th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 335-340, ISSN: 1946-1488

Conference paper

Ho CH, Yiu KFC, Huo J, Nordholm S, Luk Wet al., 2006, Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation., Publisher: CSREA Press, Pages: 184-190

Conference paper

Dimond RG, Mencer O, Luk W, 2006, Combining instruction coding and scheduling to optimize energy in system-on-FPGA, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 175-+

Conference paper

Styles H, Luk W, 2005, Compilation and management of phase-optimized reconfigurable systems, Pages: 311-316

A program phase is an interval over which the working set of the program remains more or less constant. This paper presents a dynamic optimization scheme which uses program phase information to optimize designs for reconfigurable computing. We present a mathematical formulation of the optimization problem and propose a solution which comprises of : (1) A hardware compilation scheme for generating configurations that are specialized for different phases of execution. (2) A runtime system which manages interchange of these configurations to maintain specialization between phase transitions. We report experimental results for Xilinx Virtex FPGAs involving OpenGL SPECview-perf benchmarks and demonstrate 95.39% speedup over an optimized uniform rate static design and 11.13% speedup over an optimized multi-initiation interval static design. We present a framework for a posteriori performance analysis and architectural exploration with which we (a) establish a performance upper bound under perfect phase optimization, (b) investigate sensitivity to reconfiguration time, (c) examine the quality of the proposed algorithm for phase-detection. The optimization is shown to be surprisingly insensitive to increased reconfiguration time. Faster reconfiguration yields limited benefits and performance improvements are possible upto 1 second reconfiguration time. © 2005 IEEE.

Conference paper

Yusuf S, Luk W, 2005, Bitwise optimised cam for network intrusion detection systems, Pages: 444-449

String pattern matching is a computationally expensive task, and when implemented in hardware, it can consume a large amount of resources for processing and storage. This paper presents a novel technique, based on a tree-based content addressable memory structure, for a pattern matching engine for use in a hardware-based network intrusion detection system. This technique involves hardware sharing at bit level in order to exploit powerful logic optimisations for multiple strings represented as a boolean expression. Our approach has been used to implement the entire SNORT rule set with around 12% of the area on a Xilinx XC2V8000 FPGA. The design can run at a rate of approximately 2.5 Gigabits per second, and is approximately 30% smaller in area when compared with published results. The performance of our design can be improved further by having multiple designs operating in parallel. © 2005 IEEE.

Conference paper

Leong P, Luk W, 2005, Dynamic Voltage Scaling for Commercial FPGAs, International Conference on Field Programmable Technology (FPT), Pages: 215-222

Conference paper

Lee DU, Gaffar AA, Mencer O, Luk Wet al., 2005, Optimizing hardware function evaluation, IEEE TRANSACTIONS ON COMPUTERS, Vol: 54, Pages: 1520-1531, ISSN: 0018-9340

Journal article

Chow CT, Tsui LSM, Leong PHW, Luk W, Wilton SJEet al., 2005, Dynamic voltage scaling for commercial FPGAs, International Conference on Field Programmable Technology (FPT), Pages: 173-180

Conference paper

Bower J, Mencer O, Luk W, flynn m, morf met al., 2005, Dynamically Calibrating FPGA Clock Frequencies, IEEE MICRO

Journal article

Cheung RCC, Telle NJB, Luk W, Cheung PYKet al., 2005, Customizable elliptic curve cryptosystems, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol: 13, Pages: 1048-1059, ISSN: 1063-8210

Journal article

Fahmy SA, Cheung PYK, Luk W, 2005, Novel FPGA-based implementation of median and weighted median filters for image processing, Proceedings of IEEE International Conference on Field Programmable Logic (FPL'05), Publisher: Institute of Electrical Engineers, Pages: 142-147

Conference paper

Lee DU, Luk W, Villasenor JD, Zhang GL, Leong PHWet al., 2005, A hardware Gaussian noise generator using the Wallace method, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol: 13, Pages: 911-920, ISSN: 1063-8210

Journal article

Yusuf S, Luk W, Sloman M, Dulay N, Lupu EC, Brown Get al., 2005, A combined hardware-software architecture for network flow analysis, Athens, International conference on engineering of reconfigurable systems and algorithms, 27 - 30 June 2005, Las Vegas, NV, Publisher: C S R e A Press, Pages: 149-155

Conference paper

Theerayod WT, Cheung PYK, Luk W, 2005, Hardware/software codesign, IEEE SIGNAL PROCESSING MAGAZINE, Vol: 22, Pages: 14-22, ISSN: 1053-5888

Journal article

Leong PHW, Zhang GL, Lee DU, Luk W, Villasenor JDet al., 2005, A comment on the implementation of the Ziggurat method, JOURNAL OF STATISTICAL SOFTWARE, Vol: 12, Pages: 1-4, ISSN: 1548-7660

Journal article

Yusuf S, Luk W, Sloman M, Dulay N, Lupu EC, Brown Get al., 2005, A combined hardware-software architecture for network flow analysis, International conference on engineering of reconfigurable Systems and Algorithms, Publisher: C S R e A Press, Pages: 149-155

Conference paper

Coutinho JGF, Jiang J, Luk W, 2005, Interleaving behavioral and cycle-accurate descriptions for reconfigurable hardware compilation, Los Alamitos, 13th annual ieee symposium on field-programmable custom computing machines, 18 - 20 April 2005, Napa, CA, Publisher: Ieee Computer Society, Pages: 245-254

Conference paper

Cheung RCC, Luk W, Cheung PYK, 2005, Reconfigurable elliptic curve cryptosystems on a chip, Los Alamitos, Design, automation and test in europe conference and exhibition (DATE 05), Munich, Germany, 7 - 11 March 2005, Publisher: IEEE Computer Soc, Pages: 24-29

Conference paper

Cheung C, Lee D, Mencer O, Cheung PY, Luk Wet al., 2005, Automating Custom-Precision Function Evaluation for Embedded Processors, ACM/IEEE International Conference on Compilers, Architecture, and\r\nSynthesis for Embedded Systems (CASES), San Francisco, Sept, 2005

Conference paper

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