Publications
620 results found
Lee DU, Luk W, Villasenor J, et al., 2003, Non-uniform segmentation for hardware function evaluation, Berlin, 13th international conference on field-programmable logic and applications (FPL 2003), Lisbon, Portugal, 1 - 3 September 2003, Publisher: Springer-Verlag Berlin, Pages: 796-807
Wiangtong T, Cheung PYK, Luk W, 2002, Comparing three heuristic search methods for functional partitioning in hardware-software codesign, DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, Vol: 6, Pages: 425-449, ISSN: 0929-5585
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- Citations: 85
Melis WJC, Cheung PY, Luk W, 2002, Image registration of real-time broadcast video using the UltraSONIC reconfigurable computer, Berlin, 12th international conference on field-programmable logic and applications, Montpeller, France, 2002, Publisher: Springer-Verlag, Pages: 1148-1151
Melis WJC, Cheung PY, Luk W, 2002, Image registration of real-time broadcast video using the UltraSONIC reconfigurable computer, Berlin, 12th international conference on field-programmable logic and applications, Montpeller, France, 2 - 4 September 2002, Publisher: Springer-Verlag Berlin, Pages: 1148-1151
Coutinho JGF, Luk W, Weinhardt M, 2002, Optimising parallel programs for hardware implementation, Bellingham, Conference on reconfigurable technology - FPGAs and reconfigurable processors for computing and communications IV, Boston, Massachusetts, 2002, Publisher: Spie-Int Society Optical Engineering, Pages: 60-70
Gaffar AA, Luk W, Cheung PYK, et al., 2002, Automating customisation of floating-point designs, 12th International Conference on Field-Programmable Logic and Applications, Publisher: SPRINGER-VERLAG BERLIN, Pages: 523-533, ISSN: 0302-9743
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- Citations: 8
Lee TK, Yusuf S, Luk W, et al., 2002, Development framework for firewall processors, New York, IEEE international conference on field-programmable technology (FPT), Chinese University of Hong Kong, New Territories, Peoples Republic of China, 2002, Publisher: IEEE, Pages: 352-355
Jun J, Luk W, Rueckert D, 2002, FPGA-based computation of free-form deformations, New York, IEEE international conference on Field-Programmable technology (FPT), Chinese University of Hong Kong, New Territories, Peoples Republic of China, 2002, Publisher: IEEE, Pages: 407-410
Gaffar AA, Mencer O, Luk W, et al., 2002, Floating-point bitwidth analysis via automatic differentiation, New York, IEEE international conference on field-programmable technology (FPT), Chinese Univ Hong Kong, New Territories, Peoples Republic of China, 2002, Publisher: IEEE, Pages: 158-165
Thomas DB, Luk W, 2002, Framework for development and distribution of hardware acceleration, Bellingham, Conference on reconfigurable technology - FPGAs and reconfigurable processors for computing and communications IV, Boston, Massachusetts, 2002, Publisher: Spie-Int Society Optical Engineering, Pages: 48-59
Styles H, Luk W, 2002, Accelerating radiosity calculations using reconfigurable platforms, Los Alamitos, 10th annual IEEE symposium on field-programmable custom computing machines, Napa, California, 2001, Publisher: IEEE Computer Soc, Pages: 279-281
Jun J, Schmidt S, Luk W, et al., 2002, Parameterising reconfigurable designs for image warping, Bellingham, Conference on reconfigurable technology - FPGAs and reconfigurable processors for computing and communications IV, Boston, Massachusetts, 2002, Publisher: Spie-Int Society Optical Engineering, Pages: 86-97
Derbyshire A, Luk W, 2002, Compiling run-time parametrisable designs, New York, IEEE international conference on field-programmable technology (FPT), Chinese Univ Hong Kong, New Territories, Peoples R China, 2002, Publisher: I e e e, Pages: 44-51
Gaffar AA, Luk W, Cheung PYK, et al., 2002, Customising floating-point designs, Los Alamitos, 10th annual IEEE symposium on field-programmable custom computing machines, Napa, California, 2001, Publisher: IEEE Computer Soc, Pages: 315-317
Coutinho JGF, Luk W, 2002, Optimising and adapting high-level hardware designs, New York, IEEE international conference on field-programmable technology (FPT), Chinese Univ Hong Kong, New Territories, Peoples R China, 2002, Publisher: IEEE, Pages: 150-157
Seng S, Luk W, Cheung PYK, 2002, Run-time adaptive flexible instruction processors, Berlin, 12th international conference on field-programmable logic and applications, Montpeller, France, 2002, Publisher: Springer-Verlag, Pages: 545-555
Fidjeland A, Luk W, Muggleton S, 2002, Scalable acceleration of inductive logic programs, New York, IEEE international conference on field-programmable technology (FPT), Chinese Univ Hong Kong, New Territories, Peoples Republic of China, 2002, Publisher: I e e e, Pages: 252-259
Lee D, Lee TK, Luk W, et al., 2002, Incremental programming for reconfigurable engines, New York, IEEE international conference on field-programmable technology (FPT), Chinese University of Hong Kong, New Territories, Peoples Republic of China, 2002, Publisher: IEEE, Pages: 411-415
Gaffar AA, Luk W, Cheung PYK, et al., 2002, Automating customisation of floating-point designs, Berlin, 12th international conference on field-programmable logic and applications, Montpeller, France, 2002, Publisher: Springer-Verlag, Pages: 523-533
Ip HMD, Low JD, Cheung PYK, et al., 2002, Strassen's matrix multiplication for customisable processors, New York, IEEE international conference on field-programmable technology (FPT), Chinese Univ Hong Kong, New Territories, Peoples Republic of China, 2002, Publisher: IEEE, Pages: 453-456
McKeever S, Luk W, Derbyshire A, 2002, Compiling hardware descriptions with relative placement information for parametrised libraries, Berlin, 4th international conference on formal methods in computer-aided design (FMCAD 2002), Portland, Oregon, Publisher: Springer-Verlag, Pages: 342-359
Luk W, Kean T, Derbyshire A, et al., 2001, Parameterized hardware libraries for configurable system-on-chip technology, CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, Vol: 26, Pages: 125-129, ISSN: 0840-8688
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- Citations: 1
Weinhardt M, Luk W, 2001, Memory access optimisation for reconfigurable systems, IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, Vol: 148, Pages: 105-112, ISSN: 1350-2387
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- Citations: 29
Guo SR, Luk W, 2001, An integrated system for developing regular array designs, JOURNAL OF SYSTEMS ARCHITECTURE, Vol: 47, Pages: 315-337, ISSN: 1383-7621
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- Citations: 7
Weinhardt M, Luk W, 2001, Pipeline vectorization, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol: 20, Pages: 234-248, ISSN: 0278-0070
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- Citations: 76
Mencer O, Boullis N, Luk W, et al., 2001, Parameterized function evaluation for FPGAs, Pages: 544-554, ISSN: 0302-9743
This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters and multipliers. We discuss trade-offs involved between (1) full-lookup tables, (2) bipartite (lookup-add) units, (3) lookup-multiply units, and (4) shift-and-add based CORDIC units. For lookup-multiply units we provide equations estimating approximation errors and rounding errors which are used to parameterize the hardware units. The resources and performance of the resulting design can be estimated given the input parameters. The method is implemented as part of the PAM-Blox module generation environment. An example shows that the lookup-multiply unit produces competitive designs with data widths up to 20 bits when compared with shift-and-add based CORDIC units. Additionally, the lookup-multiply method can be used for larger data widths when evaluating functions not supported by CORDIC.
Gause J, Reuter C, Kropp H, et al., 2001, The Effect of FPGA Granularity on Video Codec Implementations, Pages: 287-288
This paper presents an investigation of LUT-based FPGAs regarding their suitability for a particular application area using circuits which can be described in a typical HDL like Verilog or VHDL, not only synthetic benchmarks. The H.263 video codec has been chosen as benchmark example. In order to compare different FPGA architectures, a generic FPGA model and architecture independent modelling software are used. It is shown that coarse grain FPGAs give better area-speed trade-offs for large circuits whereas more fine grain devices are better suited for smaller designs.
Boullis N, Mencer O, Luk W, et al., 2001, Pipelined Function Evaluation on FPGAs, Pages: 304-306
This paper presents an approach to parameterizing pipelined designs for differentiable function evaluation using lookup tables, adders and multipliers. Trade-offs involved in implementing the lookup table as a full table or as bipartite tables are discussed. In case of implementations with a lookup table and a multiplier, equations estimating approximation errors and rounding errors can be used to parameterize the hardware unit. The method is implemented as part of the PAM-Blox module generation environment. An example shows that our approach produces competitive designs with data widths up to 20 bits when compared with shift-and-add based CORDIC units; it can be used for larger data widths when evaluating functions not supported by CORDIC.
McKeever S, Luk W, 2001, Towards provably-correct hardware compilation tools based on pass separation techniques, Pages: 212-227, ISSN: 0302-9743
This paper presents a framework for verifying compilation tools based on parametrised hardware libraries expressed in Pebble, a simple declarative language. Anapproach based on pass separation techniques is described for specifying and verifying Pebble abstraction mechanisms, such as the loop statement.We show how this approach can be used to verify the correctness of the flattening procedure in the Pebble compiler, which also results in a more efficient implementation than a non-verified version. The approach is useful for guiding compiler implementations for Pebble and related languages such as VHDL; it may also form the basis for automating the generation of provably-correct tools for hardware development. © 2001 Springer-Verlag Berlin Heidelberg.
Weinhardt M, Luk W, 2001, Task-parallel programming of reconfigurable systems, Pages: 172-181, ISSN: 0302-9743
This paper presents task-parallel programming, a style of application development for reconfigurable systems. Task-parallel programming enables efficient interaction between concurrent hardware and software tasks. In particular, it supports description of communication and computation tasks running in parallel to allow effective implementation of designs where data transfer time between hardware and software components is comparable to computation time. This approach permits precise specification of parallelism without requiring hardware design knowledge. We present language extensions for task-parallel programming, inspired by the occam and Handel languages. A compilation scheme for this method is described: the four main stages are memory mapping, channel implementation, software generation and hardware synthesis. Our techniques have been evaluated using video applications on the RC1000-PP hardware platform.
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