Imperial College London

ProfessorWayneLuk

Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@article{Koester:2011:10.1109/TVLSI.2010.2044902,
author = {Koester, M and Luk, W and Hagemeyer, J and Porrmann, M and Rueckert, U},
doi = {10.1109/TVLSI.2010.2044902},
journal = {IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS},
pages = {1048--1061},
title = {Design Optimizations for Tiled Partially Reconfigurable Systems},
url = {http://dx.doi.org/10.1109/TVLSI.2010.2044902},
volume = {19},
year = {2011}
}

RIS format (EndNote, RefMan)

TY  - JOUR
AU - Koester,M
AU - Luk,W
AU - Hagemeyer,J
AU - Porrmann,M
AU - Rueckert,U
DO - 10.1109/TVLSI.2010.2044902
EP - 1061
PY - 2011///
SN - 1063-8210
SP - 1048
TI - Design Optimizations for Tiled Partially Reconfigurable Systems
T2 - IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
UR - http://dx.doi.org/10.1109/TVLSI.2010.2044902
UR - https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000290998700011&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=a2bf6146997ec60c407a63945d4e92bb
VL - 19
ER -