Imperial College London
Professor Wayne Luk

ProfessorWayneLuk

Faculty of Engineering, Department of Computing

Professor of Computer Engineering
 
 
 
//

Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
//

Location

 

434Huxley BuildingSouth Kensington Campus

//

Summary

 

Publications

Citation

BibTex format

@inproceedings{Denholm:2014:10.1109/FPT.2013.6718377,
author = {Denholm, S and Inouet, H and Takenaka, T and Luk, W},
doi = {10.1109/FPT.2013.6718377},
pages = {322--325},
publisher = {IEEE},
title = {Application-specific customisation of market data feed arbitration},
url = {http://dx.doi.org/10.1109/FPT.2013.6718377},
year = {2014}
}
Download

RIS format (EndNote, RefMan)

TY  - CPAPER
AB  - Messages are transmitted from financial exchanges to update their members about changes in the market. As UDP packets are used for message transmission, members subscribe to two identical message feeds from the exchange to lower the risk of message loss or delay. As financial trades can be time sensitive, low latency arbitration between these market data feeds is of particular importance. Members must either provide generic arbitration for all of their financial applications, increasing latency, or arbitrate within each application which wastes resources and scales poorly. We present a reconfigurable accelerated approach for market feed arbitration operating at the network level. Multiple arbitrators can operate within a single FPGA to output customised feeds to downstream financial applications. Application-specific customisations are supported by each core, allowing different market feed messaging protocols, windowing operations and message buffering parameters. We model multiple-core arbitration and explore the scalability and performance improvements within and between cores. We demonstrate our design within a Xilinx Virtex-6 FPGA using the NASDAQ TotalView-ITCH 4.1 messaging standard. Our implementation operates at 16Gbps throughput, and with resource sharing, supports 12 independent cores, 33% more than simple core replication. A 56ns (7 clock cycles) windowing latency is achieved, 2.6 times lower than a hardware-accelerated CPU approach.
AU  - Denholm,S
AU  - Inouet,H
AU  - Takenaka,T
AU  - Luk,W
DO  - 10.1109/FPT.2013.6718377
EP  - 325
PB  - IEEE
PY  - 2014///
SP  - 322
TI  - Application-specific customisation of market data feed arbitration
UR  - http://dx.doi.org/10.1109/FPT.2013.6718377
UR  - https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000342561900042&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=1ba7043ffcc86c417c072aa74d649202
UR  - https://ieeexplore.ieee.org/abstract/document/6718377
ER  -
Download