Imperial College London
Professor Wayne Luk

ProfessorWayneLuk

Faculty of Engineering, Department of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Niu:2012:10.1109/FPL.2012.6339257,
author = {Niu, X and Jin, Q and Luk, W and Liu, Q and Pell, O},
doi = {10.1109/FPL.2012.6339257},
pages = {173--180},
title = {Exploiting run-time reconfiguration in stencil computation},
url = {http://dx.doi.org/10.1109/FPL.2012.6339257},
year = {2012}
}
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RIS format (EndNote, RefMan)

TY  - CPAPER
AB  - Stencil computation is computationally intensive and required by many applications. This paper proposes an approach to exploit run-time reconfigurability of field-programmable accelerators for stencil computation. System throughput is optimized by partitioning, analysing and scheduling tasks in applications to remove idle functions. To evaluate the proposed approach, Reverse Time Migration (RTM), a high performance application, is developed. Our optimized runtime reconfigurable solution, which targets a Virtex-6 FPGA in a Maxeler MAX3424A system, can achieves an improved throughput of 102.8 GFlop/s, up to two orders of magnitude faster than the CPU reference designs, 1.59 times faster than the best published GPU and FPGA results, and 1.45 times faster than an optimized static implementation. © 2012 IEEE.
AU  - Niu,X
AU  - Jin,Q
AU  - Luk,W
AU  - Liu,Q
AU  - Pell,O
DO  - 10.1109/FPL.2012.6339257
EP  - 180
PY  - 2012///
SP  - 173
TI  - Exploiting run-time reconfiguration in stencil computation
UR  - http://dx.doi.org/10.1109/FPL.2012.6339257
ER  -
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