ProfessorWayneLuk

Faculty of Engineering, Department of Computing

Professor of Computer Engineering

Contact

+44 (0)20 7594 8313w.luk Website

Location

434Huxley BuildingSouth Kensington Campus

Summary

Publications

Citation

BibTex format

@article{LUK:1993:10.1007/BF01880268,
author = {LUK, W},
doi = {10.1007/BF01880268},
journal = {JOURNAL OF VLSI SIGNAL PROCESSING},
pages = {7--20},
title = {PIPELINING AND TRANSPOSING HETEROGENEOUS ARRAY DESIGNS},
url = {http://dx.doi.org/10.1007/BF01880268},
volume = {5},
year = {1993}
}

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RIS format (EndNote, RefMan)

TY  - JOUR
AU  - LUK,W
DO  - 10.1007/BF01880268
EP  - 20
PY  - 1993///
SN  - 0922-5773
SP  - 7
TI  - PIPELINING AND TRANSPOSING HETEROGENEOUS ARRAY DESIGNS
T2  - JOURNAL OF VLSI SIGNAL PROCESSING
UR  - http://dx.doi.org/10.1007/BF01880268
UR  - https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:A1993KT58400002&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=a2bf6146997ec60c407a63945d4e92bb
VL  - 5
ER  -

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