Imperial College London
Professor Wayne Luk

ProfessorWayneLuk

Faculty of Engineering, Department of Computing

Professor of Computer Engineering
 
 
 
//

Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
//

Location

 

434Huxley BuildingSouth Kensington Campus

//

Summary

 

Publications

Citation

BibTex format

@inproceedings{Denholm:2014:10.1109/ASAP.2014.6868628,
author = {Denholm, S and Inoue, H and Takenaka, T and Becker, T and Luk, W},
doi = {10.1109/ASAP.2014.6868628},
pages = {36--40},
publisher = {IEEE},
title = {Low latency FPGA acceleration of market data feed arbitration},
url = {http://dx.doi.org/10.1109/ASAP.2014.6868628},
year = {2014}
}
Download

RIS format (EndNote, RefMan)

TY  - CPAPER
AB  - A critical source of information in automated trading is provided by market data feeds from financial exchanges. Two identical feeds, known as the A and B feeds, are used in reducing message loss. This paper presents a reconfigurable acceleration approach to A/B arbitration, operating at the network level, and supporting any messaging protocol. The key challenges are: providing efficient, low latency operations; supporting any market data protocol; and meeting the requirements of downstream applications. To facilitate a range of downstream applications, one windowing mode prioritising low latency, and three dynamically configurable windowing methods prioritising high reliability are provided. We implement a new low latency, high throughput architecture and compare the performance of the NASDAQ TotalView-ITCH, OPRA and ARCA market data feed protocols using a Xilinx Virtex-6 FPGA. The most resource intensive protocol, TotalView-ITCH, is also implemented in a Xilinx Virtex-5 FPGA within a network interface card. We offer latencies 10 times lower than an FPGA-based commercial design and 4.1 times lower than the hardware-accelerated IBM PowerEN processor, with throughputs more than double the required 10Gbps line rate.
AU  - Denholm,S
AU  - Inoue,H
AU  - Takenaka,T
AU  - Becker,T
AU  - Luk,W
DO  - 10.1109/ASAP.2014.6868628
EP  - 40
PB  - IEEE
PY  - 2014///
SN  - 2160-0511
SP  - 36
TI  - Low latency FPGA acceleration of market data feed arbitration
UR  - http://dx.doi.org/10.1109/ASAP.2014.6868628
UR  - https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000345737000006&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=1ba7043ffcc86c417c072aa74d649202
UR  - https://ieeexplore.ieee.org/document/6868628
ER  -
Download