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@inproceedings{Niu:2015:10.1145/2684746.2689076,
author = {Niu, X and Luk, W and Wang, Y},
doi = {10.1145/2684746.2689076},
pages = {74--83},
title = {EURECA: On-chip configuration generation for effective dynamic data access},
url = {http://dx.doi.org/10.1145/2684746.2689076},
year = {2015}
}

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TY  - CPAPER
AB  - This paper describes Effective Utilities for Run-timE Configuration Adaptation (EURECA), a novel memory architecture for supporting effective dynamic data access in reconfigurable devices. EURECA exploits on-chip configuration generation to reconfigure active connections in such devices cycle by cycle. When integrated into a baseline architecture based on the Virtex-6 SX475T, the EURECA memory architecture introduces small area, delay and power overhead. Three benchmark applications are developed with the proposed architecture targeting social networking (Memcached), scientific computing (sparse matrix-vector multiplication), and in-memory database (large-scale sorting). Compared with conventional static designs, up to 14.9 times reduction in area, 2.2 times reduction in critical-path delay, and 32.1 times reduction in area-delay product are achieved.
AU  - Niu,X
AU  - Luk,W
AU  - Wang,Y
DO  - 10.1145/2684746.2689076
EP  - 83
PY  - 2015///
SP  - 74
TI  - EURECA: On-chip configuration generation for effective dynamic data access
UR  - http://dx.doi.org/10.1145/2684746.2689076
ER  -

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