Imperial College London

ProfessorWayneLuk

Faculty of EngineeringDepartment of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@article{Guo:2013:10.1145/2641361.2641371,
author = {Guo, C and Luk, W and Vinkovskaya, E and Cont, R},
doi = {10.1145/2641361.2641371},
journal = {ACM SIGARCH Computer Architecture News},
pages = {59--64},
title = {Customisable pipelined engine for intensity evaluation in multivariate hawkes point processes},
url = {http://dx.doi.org/10.1145/2641361.2641371},
volume = {41},
year = {2013}
}

RIS format (EndNote, RefMan)

TY  - JOUR
AB - <jats:p>Hawkes processes are point processes that can be used to build probabilistic models to capture occurrence patterns of random events. They are widely used in high-frequency trading, seismic analysis and neuroscience. A critical calculation in Hawkes process models is intensity evaluation. The intensity of a point process represents the instantaneous rate of occurrence of events, but it is computationally expensive and challenging to calculate efficiently in order to make predictions using Hawkes process models. To accelerate the computation, we analyse data dependency in the intensity evaluation routine, and present a strategy to enable multiple intensities to be computed with a single pass through the data. We then design and optimise a pipelined hardware engine based on our strategy. In our experiments, an FPGA-based implementation of the proposed engine is evaluated by four case studies. This implementation achieves up to 94 times speedup over an optimised CPU implementation with one core, and 12 times speedup over a CPU with eight cores.</jats:p>
AU - Guo,C
AU - Luk,W
AU - Vinkovskaya,E
AU - Cont,R
DO - 10.1145/2641361.2641371
EP - 64
PY - 2013///
SN - 0163-5964
SP - 59
TI - Customisable pipelined engine for intensity evaluation in multivariate hawkes point processes
T2 - ACM SIGARCH Computer Architecture News
UR - http://dx.doi.org/10.1145/2641361.2641371
VL - 41
ER -