Several of our current PhD candidates and fellow researchers at the Data Science Institute have published, or in the proccess of publishing, papers to present their research.
@article{Ma:2016:10.1109/TCSII.2016.2536202,
author = {Ma, ZB and Yang, Y and Liu, YX and Bharath, AA},
doi = {10.1109/TCSII.2016.2536202},
journal = {IEEE Transactions on Circuits and Systems},
pages = {979--983},
title = {Recurrently decomposable 2-D convolvers for FPGA-based digital image processing},
url = {http://dx.doi.org/10.1109/TCSII.2016.2536202},
volume = {63},
year = {2016}
}
TY - JOUR
AB - Two-dimensional (2-D) convolution is a widely used operation in image processing and computer vision, characterized by intensive computation and frequent memory accesses. Previous efforts to improve the performance of field-programmable gate array (FPGA) convolvers focused on the design of buffering schemes and on minimizing the use of multipliers. A recently proposed recurrently decomposable (RD) filter design method can reduce the computational complexity of 2-D convolutions by splitting the convolution between an image and a large mask into a sequence of convolutions using several smaller masks. This brief explores how to efficiently implement RD based 2-D convolvers using FPGA. Three FPGA architectures are proposed based on RD filters, each with a different buffering scheme. The conclusion is that RD based architectures achieve higher area efficiency than other previously reported state-of-the-art methods, especially for larger convolution masks. An area efficiency metric is also suggested, which allows the most appropriate architecture to be selected.
AU - Ma,ZB
AU - Yang,Y
AU - Liu,YX
AU - Bharath,AA
DO - 10.1109/TCSII.2016.2536202
EP - 983
PY - 2016///
SN - 1549-7747
SP - 979
TI - Recurrently decomposable 2-D convolvers for FPGA-based digital image processing
T2 - IEEE Transactions on Circuits and Systems
UR - http://dx.doi.org/10.1109/TCSII.2016.2536202
UR - http://hdl.handle.net/10044/1/33197
VL - 63
ER -