@article{Wu:2011:10.1109/ISPSD.2011.5890863,
author = {Wu, R and Sin, JKO and Hui, SY},
doi = {10.1109/ISPSD.2011.5890863},
journal = {Proceedings of the International Symposium on Power Semiconductor Devices and ICs},
pages = {352--355},
title = {A novel silicon-embedded coreless transformer for isolated DC-DC converter application},
url = {http://dx.doi.org/10.1109/ISPSD.2011.5890863},
year = {2011}
}

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TY  - JOUR
AB  - In this paper, a novel silicon-embedded coreless transformer (SECT) is proposed and demonstrated for isolated dc-dc converter applications. By embedding two interleaved thick Cu coils in the bottom layer of the Si substrate, the designed 2 mm2 SECT can achieve a maximum transformer efficiency of 85% at 50 MHz. Compared to the on-silicon coreless power transformer reported earlier for 0.5 W isolated dc-dc conversion at 170 MHz with a transformer efficiency of over 70%, the much lower operating frequency of the SECT allows the power losses of the power MOSFETs and Schottky diodes to be reduced by around 50%, leading to a converter loss reduction of 38%. Since only 4 vias are opened at the top layer of the substrate, most of the top layer of the substrate can be used for power IC implementation to achieve efficient monolithic integration. Experimental results show that the SECT provides a maximum transformer efficiency of 73% at 50 MHz, which is lower than expected and due to the non-optimized isolation oxide used. © 2011 IEEE.
AU  - Wu,R
AU  - Sin,JKO
AU  - Hui,SY
DO  - 10.1109/ISPSD.2011.5890863
EP  - 355
PY  - 2011///
SN  - 1063-6854
SP  - 352
TI  - A novel silicon-embedded coreless transformer for isolated DC-DC converter application
T2  - Proceedings of the International Symposium on Power Semiconductor Devices and ICs
UR  - http://dx.doi.org/10.1109/ISPSD.2011.5890863
ER  - 

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