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  • Conference paper
    Guven O, Eftekhar A, Kindt W, Constandinou TGet al., 2017,

    Low-power real-time ECG baseline wander removal: hardware implementation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1571-1574

    This paper presents a hardware realisation of a novel ECG baseline drift removal that preserves the ECG signal integrity. The microcontroller implementation detects the fiducial markers of the ECG signal and the baseline wander estimation is achieved through a weighted piecewise linear interpolation. This estimated drift is then removed to recover a “clean” ECG signal without significantly distorting the ST segment. Experimental results using real data from the MIT-BIH Arrhythmia Database (recording 100 and 101) with added baseline wander (BWM1) from the MIT-BIH Noise Stress Database show an average root mean square error of 34.3uV (mean), 30.4u V (median) and 18.4uV (standard deviation) per heart beat.
  • Conference paper
    Gao C, Ghoreishizadeh S, Liu Y, Constandinou TGet al., 2017,

    On-chip ID generation for multi-node implantable devices using SA-PUF

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 678-681

    This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 m CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.
  • Conference paper
    Haci D, Liu Y, Constandinou TG, 2017,

    32-channel ultra-low-noise arbitrary signal generation platform for biopotential emulation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 698-701

    This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10kHz bandwidth, 110dB dynamic range and uV-level output noise.
  • Conference paper
    Maslik M, Liu Y, Lande TS, Constandinou TGet al., 2017,

    A charge-based ultra-low power continuous-time ADC for data driven neural spike processing

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1420-1423

    The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75uW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ~4uW. The circuit has been implemented in a commercially available 0.35um CMOS technology with core occupying a footprint of 0.12 sq.mm
  • Conference paper
    Leene L, Constandinou TG, 2017,

    A 0.5V time-domain instrumentation circuit with clocked and unclocked ΔΣ operation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 2619-2622, ISSN: 2379-447X

    This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nanometre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which isnot well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked ΔΣ behavior which is useful on-chip characterizationand interfacing with synchronous systems. A 0.5V instrumentation system is implemented using a 65nm TSMC technology to realize a highly compact footprint that is 0.006mm2 in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 Vrms input referred noise for the given 810nW total system power budget corresponding to an NEF of 1.64.
  • Journal article
    Ghoreishizadeh S, Haci D, Liu Y, Donaldson N, Constandinou TGet al., 2017,

    Four-Wire Interface ASIC for a Multi-Implant Link

    , IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Pages: 3056-3067, ISSN: 1549-8328

    This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical ‘optrodes’ that facilitate a bidirectional neural interface (electrical recording, optical stimulation), and chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate(up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) which is superimposed on a power carrier. On-chip power management provides an unregulated 5V DC supply with up to 2.5mA output current for stimulation, and two regulated voltages (3.3V and 3V) with 60 dB PSRR for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35 um CMOS technology, occupying 1.5mm2 silicon area,and consumes a quiescent current of 91.2u A. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.
  • Conference paper
    Troiani F, Nikolic K, Constandinou TG, 2017,

    Optical coherence tomography for compound action potential detection: a computational study

    , SPIE/OSA European Conferences on Biomedical Optics (ECBO), Publisher: Optical Society of America / SPIE, Pages: 1-3

    The feasibility of using time domain optical coherence tomography (TD-OCT) to detect compound action potential in a peripheral nerve and the setup characteristics, are studied through the use of finite-difference time-domain (FDTD) technique.
  • Conference paper
    Luo JW, Firfilionis D, Ramezani R, Dehkhoda F, Soltan A, Degenaar P, Liu Y, Constandinou Tet al., 2017,

    Live demonstration: A closed-loop cortical brain implant for optogenetic curing epilepsy

    A closed-loop optogenetic system for curing epilepsy is presented in this work. As it shown at figure 1, the system consists of a cortical brain implant with LEDs and recording electrodes, a customer designed CMOS chip[1][2][3] and a controller. The brain activities are recorded by the implant with recording electronics in a CMOS chip, the signals are processed by the controller, and the results are send back to the CMOS chip for delivering LED stimulation commands.
  • Journal article
    Leene L, Constandinou TG, 2017,

    A 0.016² 12b ΔΣSAR With 14fJ/conv. for ultra low power biosensor arrays

    , IEEE Transactions on Circuits and Systems. Part 1: Regular Papers, Vol: 64, Pages: 2655-2665, ISSN: 1549-8328

    The instrumentation systems for implantable brain-machine interfaces represent one of the most demanding applications for ultra low-power analogue-to-digital-converters (ADC) to date. To address this challenge, this paper proposes a ΔΣSAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0-2 MASH topology. This configuration uses a specialized FIR window to decimate the ΔΣ modulator output and reject mismatch errors from the SAR quantizer, which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision. A fully differential prototype was fabricated using 0.18 μm CMOS to demonstrate 10.8 ENOB precision with a 0.016 mm² silicon footprint. Moreover, a 14 fJ/conv figure-of-merit can be achieved, while resolving signals with the maximum input amplitude of ±1.2,Vpp sampled at 200 kS/s. The ADC topology exhibits a number of promising characteristics for both high speed and ultra low-power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio, which are critical parameters for many sensor applications.
  • Conference paper
    Ghoreishizadeh S, Haci D, Liu Y, Constandinou Tet al., 2017,

    A 4-wire interface SoC for shared multi-implant power transfer and full-duplex communication

    , IEEE Latin American symposium on Circuits and Systems (LASCAS), Publisher: IEEE, Pages: 49-52, ISSN: 2473-4667

    This paper describes a novel system for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires a single Chest Device be connected to a Brain Implant consisting of multiple identical optrodes that record neural activity and provide closed loop optical stimulation. The interface is integrated within each optrode SoC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (1.6 Mbps) that is higher than that of the chest-to-head downlink (100kbps) superimposed on a power carrier. On-chip power management provides an unregulated 5 V DC supply with up to 2.5 mA output current for stimulation, and a regulated 3.3 V with 60 dB PSRR for recording and logic circuits. The circuit has been implemented in a 0.35 μm CMOS technology, occupying 1.4 mm 2 silicon area, and requiring a 62.2 μA average current consumption.
  • Conference paper
    Luan S, Williams I, De-Carvalho F, Grand L, Jackson A, Quian Quiroga R, Constandinou TGet al., 2017,

    Standalone headstage for neural recording with real-time spike sorting and data logging

    , BNA Festival of Neuroscience, Publisher: The British Neuroscience Association Ltd
  • Conference paper
    Sundarasaradula Y, Constandinou TG, Thanachayanont A, 2017,

    A 6-bit, two-step, successive approximation logarithmic ADC for biomedical applications

    , IEEE International Conference on Electronics, Circuits and Systems (ICECS), Publisher: IEEE, Pages: 25-28

    This paper presents the design and realization of a novel low-power 6-bit successive approximation logarithmic ADC for biomedical applications. A two-step successive approximation method is proposed to obtain a piecewise-linear approximation of the desired logarithmic transfer function. The proposed ADC has been designed and simulated using process parameters from a standard 0.35 μm 2P4M CMOS technology with a single 1.8 V power supply voltage. Simulation results show that, at a sampling rate of 25 kS/s, the proposed ADC consumes 4.36 μW to 14.6 μW (proportional to input amplitudes). The proposed ADC achieves 18.6 pJ/conversion-step, maximum INL of 0.45 LSB, an ENOB of 4.97-bits, and SNDR of 31.7 dB with 1 V full-scale input range.
  • Conference paper
    Leene L, Constandinou TG, 2017,

    A 0.45V continuous time-domain filter using asynchronous oscillator structures

    , IEEE International Conference on Electronics, Circuits and Systems (ICECS), Publisher: IEEE, Pages: 49-52

    This paper presents a novel oscillator based filter structure for processing time-domain signals with linear dynamics that extensively uses digital logic by construction. Such a mixed signal topology is a key component for allowing efficient processing of asynchronous time encoded signals that does not necessitate external clocking. A miniaturized primitive is introduced as analogue time-domain memory that can be modelled, synthesized, and incorporated in closed loop mixed signal accelerators to realize more complex linear or non-linear computational systems. This is contextualized by demonstrating a compact low power filter operating at 0.45 V in 65 nm CMOS. Simulation results are presented showing an excess of 50 dB dynamic range with a FOM of 7fJ/pole which promises an order of magnitude improvement on state-of-the-art filters in nanometre CMOS.
  • Conference paper
    Leene L, Constandinou TG, 2017,

    A 2.7uW/Mips, 0.88GOPS/mm^2 Distributed Processor for Implantable Brain Machine Interfaces

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 360-363

    This paper presents a scalable architecture in 0.18u m CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributedprocessor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7uW/MIPS with a total chip area of 1.37mm2. This configuration executes 1024 instructions on each core at 20MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain.
  • Conference paper
    Williams I, Rapeaux A, Liu Y, Luan S, Constandinou TGet al., 2017,

    A 32-channel bidirectional neural/EMG interface with on-chip spike detection for sensorimotor feedback

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 528-531

    This paper presents a novel 32-channel bidirectional neural interface, capable of high voltage stimulation and low power, low-noise neural recording. Current-controlled biphasic pulses are output with a voltage compliance of 9.25V, user configurable amplitude (max. 315 uA) & phase duration (max. 2 ms). The low-voltage recording amplifiers consume 23 uW per channel with programmable gain between 225 - 4725. Signals are10-bit sampled at 16 kHz. Data rates are reduced by granular control of active recording channels, spike detection and event-driven communication, and repeatable multi-pulse stimulation configurations.
  • Conference paper
    Frehlick Z, Williams I, Constandinou TG, 2017,

    Improving Neural Spike Sorting Performance Using Template Enhancement

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 524-527

    This paper presents a novel method for improving the performance of template matching in neural spike sorting for similar shaped spikes, without increasing computational complexity. Mean templates for similar shaped spikes are enhanced to emphasise distinguishing features. Template optimisation is based on the variance of sample distributions. Improved spike sorting performance is demonstrated on simulated neural recordings with two and three neuron spike shapes. The method is designed for implementation on a Next Generation Neural Interface (NGNI) device at Imperial College London.
  • Conference paper
    Luan S, Liu Y, Williams I, Constandinou TGet al., 2017,

    An Event-Driven SoC for Neural Recording

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 404-407

    This paper presents a novel 64-channel ultra-low power/low noise neural recording System-on-Chip (SoC) featuring a highly reconfigurable Analogue Front-End (AFE) and block-selectable data-driven output. This allows a tunable bandwidth/sampling rate for extracting Local Field Potentials (LFPs)and/or Extracellular Action Potentials (EAPs). Realtime spike detection utilises a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The 64-channels are organised into 16 sets of 4-channel recording blocks, with each block having a dedicated 10-bit SAR ADC that is time division multiplexed among the 4 channels. Eachchannel can be individually powered down and configured for bandwidth, gain and detection threshold. The output can thus combine continuous-streaming and event-driven data packets with the system configured as SPI slave. The SoC is implemented in a commercially-available 0.35u m CMOS technology occupying a silicon area of 19.1mm^2 (0.3mm^2 gross per channel) and requiring 32uW/channel power consumption (AFE only).
  • Conference paper
    Lauteslager T, Tommer M, Kjelgard KG, Lande TS, Constandinou TGet al., 2017,

    Intracranial Heart Rate Detection Using UWB Radar

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 119-122

    Microwave imaging is a promising technique for noninvasive imaging of brain activity. A multistatic array of body coupled antennas and single chip pulsed ultra-wideband radars should be capable of detecting local changes in cerebral blood volume, a known indicator for neural activity. As an initialverification that small changes in the cerebrovascular system can indeed be measured inside the skull, we recorded the heart rate intracranially using a single radar module and two body coupled antennas. The obtained heart rate was found to correspond to ECG measurements. To confirm that the measured signal was indeed from within the skull, we performed simulations to predict the time-of-flight of radar pulses passing through differentanatomical structures of the head. Simulated time-of-flight through the brain corresponded to the measured delay of heart rate modulation in the radar signal. The detection of intracranial heart rate using microwave techniques has not previously been reported, and serves as a first proof that functional neuroimaging using radar could lie within reach.
  • Journal article
    De Marcellis A, Palange E, Nubile L, Faccio M, Di Patrizio Stanchieri G, Constandinou Tet al., 2016,

    A pulsed coding technique based on optical UWB modulation for high data rate low power wireless implantable biotelemetry

    , Electronics, Vol: 5, Pages: 1-10, ISSN: 2079-9292

    This paper reports on a pulsed coding technique based on optical Ultra-wideband (UWB)modulation for wireless implantable biotelemetry systems allowing for high data rate link whilstenabling significant power reduction compared to the state-of-the-art. This optical data codingapproach is suitable for emerging biomedical applications like transcutaneous neural wirelesscommunication systems. The overall architecture implementing this optical modulation techniqueemploys sub-nanosecond pulsed laser as the data transmitter and small sensitive area photodiode asthe data receiver. Moreover, it includes coding and decoding digital systems, biasing and drivinganalogue circuits for laser pulse generation and photodiode signal conditioning. The complete systemhas been implemented on Field-Programmable Gate Array (FPGA) and prototype Printed CircuitBoard (PCB) with discrete off-the-shelf components. By inserting a diffuser between the transmitterand the receiver to emulate skin/tissue, the system is capable to achieve a 128 Mbps data rate with abit error rate less than 10 9 and an estimated total power consumption of about 5 mW correspondingto a power efficiency of 35.9 pJ/bit. These results could allow, for example, the transmission of an800-channel neural recording interface sampled at 16 kHz with 10-bit resolution.
  • Conference paper
    De Marcellis A, Palange E, Faccio M, Nubile L, Di Patrizio Stanchieri G, Constandinou TGet al., 2016,

    A new optical UWB modulation technique for 250Mbps wireless link in implantable biotelemetry systems

    , Eurosensors, Publisher: Elsevier: Creative Commons Attribution Non-Commercial No-Derivatives License, Pages: 1676-1680, ISSN: 1877-7058

    We propose a new UWB modulation technique for wireless optical communications in transcutaneous biotelemetry. The solution, based on the generation of sub-nanoseconds laser pulses, allows for a high data rate link whilst achieving a significant power reduction (energy per bit) compared to the state-ofthe- art. These features make this particularly suitable for emerging biomedical applications such as implantable neural/biosensor systems. The relatively simple architecture consists of a transmitter and receiver that can be integrated in a standard CMOS technology in a compact Silicon footprint (lower than 1mm^2 in a 0.18μm technology). These parts, optimised for low-voltage/low-power operation, include coding and decoding digital systems, biasing and driving analogue circuits for laser pulse generation and photodiode signal conditioning. Experimental findings with prototype PCBs have validated the new paradigm showing the system capabilities to achieve a BER less than 10^-9 with data rate up to 250Mbps and estimated total power consumption lower than 5mW.

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