The second 2-day workshop on Novel Architecture and Novel Design Automation (NANDA) will take place at Imperial College on 11-12 September 2023, hosted by Imperial’s Centre for High-performance Embedded and Distributed Systems. The purpose of this workshop is to invite renowned experts in the two areas of novel computer architecture and novel design automation tools, to present their latest advances, and to provide a forum to spark new ideas.

Our aim is to make this event a really valuable landmark in the calendar for research in these areas, with a priority on bringing interesting people together for interesting discussions!

Participation is open to all (registration details and costs to be announced). Attending with a poster will make the experience more valuable! You are also warmly encouraged to forward this invitation to students, colleagues and collaborators, in academia and in industry.

We hope you'll be able to join us in September in London!

Registration

You may register to attend the workshop by going to our Cassyni site and clicking on the "Register to attend" button at the top of the page.

• Early Full Registration (on or before 1st September) £300
• Full Registration £350
• Student Registration £150

Invited Speakers

• Rob Dimond, Arm — Domain Specific Compute in the Datacentre – Opportunities and Challenges
• Tobias Becker, Maxeler Technologies — Scalable Architectures for Large Language Models
• Alastair Donaldson, Imperial College — Can You Trust Your Compiler? Recent Developments in Automated Testing of Compilation and Verification Tools
• Kerstin Eder, University of Bristol — Energy Transparency - More Power to Software Developers!
• Steve Furber, University of Manchester — Building Brains
• Lachlan J. Gunn, Aalto University — Design Across Layers: Achieving More by Joining Hardware, Software, and Cryptography
• Adam Hillier & Ngân Vũ, DeepMind — Learning to Design Efficient Logic Circuits
  
• Tim Jones, University of Cambridge — ParaSol: Thread-Level Speculation for Modern High-Performance Cores
• Ruby B. Lee, Princeton University — Speech-oriented Computers
  
• Miriam Leeser, Northeastern University — Pets vs Cattle:  Heterogeneous Systems in the 21st Century
• Philip Leong, Sydney University — Acceleration of Cyclostationary Signal Processing Algorithms
• Tom Melham, University of Oxford — Integrating Symbolic Simulation of C/C++ into a Comprehensive EDA Verification Environment
• Subhasish Mitra, Stanford University — The Future of Hardware Technologies for Computing
• Robert Mullins, University of Cambridge — lowRISC: Building a Digital Commons using Collaborative Engineering
• Magnus Myreen, Chalmers University of Technology — First Steps in Verified Placement, Routing and Timing
• Michael O’Boyle, Edinburgh University — Rethinking How We Build Compilers: Synthesis and Neural Machine Translation
• Kunle Olukotun, Stanford University — Computing in the Large Language Model Era
• Laura Pozzi, USI Lugano — Approximate Logic Synthesis: a New Dimension for the Synthesis of Digital Circuits
• Mary Sheeran, Chalmers University of Technology — Functional Hardware Design and Verification Revisited  
• Jens Teubner, TU Dortmund — DB/OS Co-Design in the MxKernel Project
• Ahmad Yasin, Intel — Towards a Structured Software Performance Tuning Process

Call for Posters

We would like to invite you to submit a poster for presentation at this workshop - simply to provide you with a concrete way to initiate conversations about your interests. Posters will be reviewed with a light-touch process, by a small committee of organisers and invited speakers.  Your poster can report on already-published work, work-in-progress, and speculative research ideas - on topics including, but not restricted to:

• Security, resilience and power efficiency
• ASIC and FPGA design toolchain, verification, test, synthesis
• Processor microarchitecture
• Instruction set design, specification, verification, test
• Memory system architecture, parallelism, coherency, disaggregation, PIM
• Datapath synthesis, approximate computing, precision optimisation
• Accelerator synthesis, offload, workload analysis and partitioning
• Performance instrumentation, simulation methodology, design optimisation
• Hardware/software co-design, static and dynamic analysis enabling architecture
• Domain-specific optimisation

For guidance on topics of interest, check out the talks at NANDA’22 via the link above, or email (p.kelly@imperial.ac.uk) and ask.

How to submit your poster:

• Submissions may be made at any time up to 30 August 2023.
• We aim to notify acceptance of posters as quickly as possible, and early submissions are encouraged.
• Please submit pdf posters for review via Easychair.
• If your poster submission is accepted, please bring your paper poster with you to the event.  You may, of course, bring a revised and improved version!

Poster design and formatting

• You will need to provide a short abstract when submitting your poster, which we will use in the online programme
• Posters should be no larger than A0 size, for presentation in landscape orientation
• Make sure the title, authors and affiliations are clearly shown at the top
• Text should be easily readable from 2m (six feet) away
• Your objective is to get the right people to engage with you in-person - you don’t have to tell the whole story - but you do need to hook the viewer within 60 seconds.  The right image is probably the key!

There will be no formal proceedings but there will be a web-based record of the event, and posters can, optionally, be included there, after the workshop.